The present invention relates to a semiconductor memory device and, more particularly, to a method for fabricating a semiconductor memory device, in which a fabricating step of removing a seed layer can be omitted.
With the recent progress of film deposition techniques, applications of a nonvolatile memory cell using a ferroelectric thin film have increasingly been developed. This nonvolatile memory cell is a high-speed rewritable nonvolatile memory cell utilizing the high-speed polarization/inversion and the residual polarization of the ferroelectric capacitor thin film.
Therefore, a ferroelectric random access memory (FeRAM) having a capacitor thin film with ferroelectric properties, such as strontium bismuth tantalate (SBT) and lead zirconate titanate (PZT), is increasingly used for a capacitor, because it assures a low-voltage and high-speed performance, and does not require periodic refresh to prevent loss of information during standby intervals like a dynamic random access memory (DRAM).
Since a ferroelectric material has a dielectric constant ranging in value from hundreds to thousands, and stabilized residual polarization property at room temperature, it is being applied to the non-volatile memory device as the capacitor thin film. When employing the ferroelectric capacitor thin film in the non-volatile memory device, information data are stored by polarization of dipoles when an electric field is applied thereto. Even if the electric field is removed, the residual polarization remains so that one of information data, i.e., xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, can be stored.
FIGS. 1A to 1C are cross-sectional views showing sequential steps for fabricating a conventional FeRAM device.
Referring to FIG. 1A, a transistor (not shown) is formed on a semiconductor substrate 10 to thereby provide a semiconductor structure. Then, a first interlayer insulating layer 12 is selectively etched to define a contact hole which exposes a source/drain region 11 contained in the transistor. Thereafter, a plug is formed by stacking a polysilicon plug 13, TiSi2 layer 14 and TiN layer 15, and a seed layer 16 is formed on the entire resulting structure.
Referring to FIG. 1B, the seed layer 16 is selectively etched to form a patterned seed layer 16A.
Referring to FIG. 1C, a lower electrode 17 is formed on the patterned seed layer 16A by electrochemical deposition (ECD), and then a ferroelectric layer 18 and an upper electrode 19 are sequentially stacked thereon. Thereafter, the upper electrode 19 and the ferroelectric layer 18 are patterned to thereby form a capacitor.
As described above, when the lower electrode is formed by the ECD, the seed layer is necessarily required. Additionally, since the seed layer existing outside the lower electrode should be removed, the fabricating steps become complicated.
It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor memory device in which a fabricating step of removing a seed layer can be omitted.
In accordance with an aspect of the present invention, there is provided a method for fabricating a semiconductor memory device, comprising steps of a) providing a semiconductor structure, wherein the semiconductor structure has an insulating layer formed on a semiconductor substrate; b) forming a seed layer on an insulating layer covering the semiconductor substrate; c) forming a sacrifice layer on the seed layer; d) selectively etching the sacrifice layer to expose the seed layer, thereby defining an opening; e) forming a lower electrode layer on the seed layer disposed within the opening; f) removing the sacrifice layer to expose the lower electrode and a portion of the seed layer not covered by the lower electrode; g) oxidizing the exposed portion of the seed layer to form an insulating layer; and h) sequentially forming a ferroelectric layer and an upper electrode on the lower electrode.
In accordance with another aspect of the present invention, there is provided a method for fabricating a semiconductor memory device, comprising steps of a) providing a semiconductor structure, wherein the semiconductor structure includes a transistor formed on a semiconductor substrate; b) forming an interlayer insulating layer on the semiconductor structure; c) exposing a source/drain region contained in the transistor by selectively etching the interlayer insulating layer, thereby defining a contact hole; d) forming a plug within the contact hole; e) forming a seed layer on an entire resulting structure; f) forming a sacrifice layer on the seed layer; g) exposing the seed layer by selectively etching the sacrifice layer to thereby define an opening for defining a lower electrode region; h) forming a lower electrode on the seed layer disposed within the opening; i) removing the sacrifice layer to expose the lower electrode and a portion of the seed layer not covered by the lower electrode; j) oxidizing the exposed portion of the seed layer to form an insulating layer; and k) sequentially forming a ferroelectric layer and an upper electrode on the lower electrode.